1. Field of the Invention
The present invention generally relates to a method of forming a semiconductor device.
Priority is claimed on Japanese Patent Application No. 2009-287802, Dec. 18, 2009, the content of which is incorporated herein by reference.
2. Description of the Related Art
In transistors with a planar structure in which a substrate surface is used as a channel in the related art, the miniaturization of semiconductor devices has led to difficulty in suppressing a short channel effect, and desired transistor characteristics cannot be obtained.
Japanese Unexamined Patent Application, First Publications, Nos. JP-A-2006-339476 and JP-A-2007-081095 disclose using groove gate transistors to suppress the short channel effect.
In the groove gate transistors described in Japanese Unexamined Patent Application, First Publication, No. JP-A-2006-339476 and JP-A-2007-081095, surfaces of grooves formed in a semiconductor substrate are used as channels. Increase in the depth dimension of the groove can suppress the short channel effect, even the horizontal dimensions of the groove are decreased.